Display devices have become thinner and larger as industrial utilization has increased. Among the various types of flat panel display (FPD) devices, liquid crystal display (LCD) devices and plasma display panel (PDP) devices are widely used. LCD devices are widely used as monitors for notebook computers and desktop computers because of characteristics such as light weight, portability and low power consumption. Specifically, active matrix type LCD devices having thin film transistors (TFTs) as switching elements have been researched and developed due to the quality of the display of moving images.
FIG. 1 is a schematic block diagram of a liquid crystal display device according to the related art, and FIG. 2 is a schematic view showing a liquid crystal panel of the liquid crystal display device according to the related art. In FIGS. 1 and 2, the liquid crystal display device includes a liquid crystal panel 2 and a liquid crystal module (LCM) driving circuit 26. The LCM driving circuit 26 includes an interface 10, a timing controller 12, a source voltage generator 14, a reference voltage generator 16, a data driver 18 and a gate driver 20. The data driver 18 may also be referred to as a source driver, which may be distinguished from the source voltage generator 14. RGB data and timing sync signals, such as clock signals, horizontal sync signals, vertical sync signals and data enable signals may be input from a driving system (not shown) such as a personal computer to the interface 10. The interface 10 outputs the RGB data and the timing sync signals to the timing controller 12. For example, a low voltage differential signal (LVDS) interface and transistor-transistor logic (TTL) interface may be used for transmission of the RGB data and the timing sync signals. In addition, the interface 10 may be integrated on a single chip together with the timing controller 12.
A plurality of gate lines “GL1” to “GLn” and a plurality of data lines “DL1” to “DLm” are formed on the liquid crystal panel 2 and are driven respectively by the gate driver 20 and the data driver 18. The plurality of gate lines “GL1” to “GLn” and the plurality of data lines “DL1” to “DLm” cross each other to define a plurality of pixel regions “P.” For each pixel region P, a thin film transistor “TFT” is connected to the corresponding gate line and the corresponding data line. In addition, a liquid crystal capacitor “LC” connected to the thin film transistor “TFT” is formed in each pixel region “P.” The pixel formed at the liquid crystal capacitor “LC” is turned on/off by the thin film transistor “TFT,” thereby modulating transmittance of incident light for the displaying of images.
The timing controller 12 generates data control signals for the data driver 18 including a plurality of data integrated circuits (ICs), and gate control signals for the gate driver 20 including a plurality of gate ICs. In addition, the timing controller 12 outputs data signals to the data driver 18. The reference voltage generator 16 generates reference voltages of a digital-to-analog converter (DAC) used in the data driver 18. The reference voltages are set up according to transmittance-voltage characteristics of the liquid crystal panel 2. The data driver 18 determines the reference voltages for the data signals according to the data control signals and outputs the determined reference voltages to the liquid crystal panel 2 to adjust a rotation angle of liquid crystal molecules.
The gate driver 20 controls ON/OFF operation of the thin film transistors (TFTs) in the liquid crystal panel 2 according to the gate control signals from the timing controller 12. Accordingly, the data signals from the data driver 18 are supplied to pixels in the pixel regions of the liquid crystal panel 2 through the TFTs. The source voltage generator 14 supplies source voltages to elements of the LCD device and a common voltage to the liquid crystal panel 2. Although not shown in FIGS. 1 and 2, a backlight unit including at least one lamp is disposed under the liquid crystal panel 2 to supply a light to the liquid crystal panel.
The LCD device includes a power management unit such as the source voltage generator 14 to supply units of the LCD device with source power for operation. FIG. 3 is a schematic block diagram showing a source voltage generator for a liquid crystal display device according to the related art. In FIG. 3, a source voltage generator 14 generates source voltages such as a driving voltage, a gate high voltage Vgh, a gate low voltage Vgl, a gamma reference voltage Vγ and a common voltage Vcom based on an external voltage Vcc from an external system. The driving voltages are supplied to the timing controller 12, the data driver 18, the gate driver 20 and the reference voltage generator 16 (of FIG. 1). Accordingly, the source voltage generator 14 includes a power control integrated circuit (P-IC) 14a, a driving voltage generator 14b, a gate high voltage generator 14c, a gate low voltage generator 14d and a shutdown controller 14e. 
The P-IC 14a has an IC type including a plurality of circuital elements. The P-IC 14a generates supply voltages for the driving voltage generator 14b, the gate high voltage generator 14c and the gate low voltage generator 14d using the external voltage Vcc of about 0V to about 3.3V. The driving voltage generator 14b generates a driving voltage Vdd of about 15V using the external voltage Vcc. The driving voltage Vdd is supplied to the data driver 18. In addition, the driving voltage Vdd is distributed by a distribution resistor to be the common voltage. The common voltage Vcom is supplied to a common electrode of the liquid crystal panel 2 through a pad (not shown). A liquid crystal layer of the liquid crystal panel 2 is driven by the driving voltage Vdd and the common voltage Vcom.
The gate high voltage generator 14c generates a gate high voltage Vgh of about 25V to about 27V using the external voltage Vcc. The gate high voltage Vgh is supplied to the gate driver 20 (of FIG. 2) and is used for a gate signal that is applied to the plurality of gate lines GL1 to GLn (of FIG. 2) by the gate driver 20. The gate low voltage generator 14d generates a gate low voltage Vgl of about −5V using the external voltage Vcc. The gate low voltage Vgl is supplied to the gate driver 20 and is used for the gate signal.
The shutdown controller 14e receives a dynamic power management (DPM) signal from the timing controller 12 (of FIG. 1) and controls a shutdown of the P-IC 14a. Accordingly, the P-IC 14a has a shutdown signal input terminal (not shown). For example, when a shutdown signal of about 0V to about 0.7V is inputted to the P-IC 14a, the P-IC 14a may be shut down and the supply voltages for operating the driving voltage generator 14b, the gate high voltage generator 14c and the gate low voltage generator 14d may be not generated. As a result, operation of the source voltage generator 14 is substantially stopped and the LCD device is powered off based on receipt of the shutdown signal inputted to the P-IC 14a. 
In the LCD device with the source voltage generator 14, static electricity induced at the liquid crystal panel 2 may be discharged to the source voltage generator 14 through the gate driver 20 (of FIG. 1). The static electricity may interfere with the generation of the gate high voltage Vgh and the gate low voltage Vgl in the source voltage generator 14. For example, the gate high voltage generator 14c may not generate the normal gate high voltage Vgh of about 25V to about 27V but may output an abnormal gate high voltage of about 7V. The abnormal gate high voltage that differs from the normal gate high voltage Vgh may result in deterioration of an image quality of the liquid crystal panel 2 (of FIG. 1). For example, the abnormal gate high voltage may result in an abnormality on the display, such as a horizontal stripe.